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Ordering number : EN*5537A
CMOS IC
LC78857V
Digital Audio D/A Converter IC with On-Chip Digital Filters
Preliminaly Overview
The LC78857V is a sigma-delta type D/A converter for use in digital audio systems. It provides both digital and analog filters on chip.
Package Dimensions
unit: mm 3175A-SSOP24
[LC78857V]
Features
* Built-in 8x oversampling digital filters: 3-stage FIR structure (31st order, 11th order, and 3rd order filters) * Analog low-pass filter * Digital deemphasis (handles Fs = 44.1 kHz operation) * Digital attenuator * Soft muting * Supports a 384fs system clock rate. * 5-V single-voltage power supply * Fabricated in a silicon gate CMOS process.
SANYO: SSOP24
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter Maximum supply voltage Input voltage Output voltage Operating temperature Storage temperature Symbol VDD max VIN VOUT Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -30 to +75 -40 to +125 Unit V V V C C
Allowable Operating Ranges at Ta = 25C
Parameter Supply voltage Input voltage Operating temperature Symbol VDD TIN Topr Conditions Ratings min 3.5 0 -30 typ 5.0 max 5.5 VDD +75 Unit V V C
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D3097HA (OT) No. 5537-1/11
LC78857V DC Characteristics at Ta = -30 to 75C, VDD = 3.5 to 5.5 V, VSS = 0 V
Parameter Input high-level voltage (1) Input low-level voltage (1) Input high-level voltage (2) Input low-level voltage (2) Output high-level voltage Output low-level voltage Input leakage current Allowable power dissipation Symbol VIH1 VIL1 VIH2 VIL2 VOH VOL IL Pd Pin 15 Pin 15 Pins 6, 7, 8, 9, 10, 11, 14, 18, and 19 Pins 6, 7, 8, 9, 10, 11, 14, 18, and 19 IOH = -3 mA, pin 17 IOL = 3 mA, pin 17 VI = VSS, VDD: Pins 6, 7, 8, 9, 10, 11, 14, 15, 18, and 19 VDD = 5.0 V -25 135 2.4 0.4 25 200 2.2 0.8 Conditions Ratings min 0.7 VDD 0.3 VDD typ max Unit V V V V V V A mW
AC Characteristics at Ta = -30 to 75C, VDD = 3.5 to 5.5 V, VSS = 0 V
Parameter Oscillator frequency BCLK frequency BCLK pulse width BCLK rise time BCLK fall time DATA setup time DATA hold time LRCK setup time LRCK hold time SH/EMP pulse period SH/EMP pulse width SH/EMP rise time SH/EMP fall time LAT/ND pulse width Latch pulse input time LAT/ND rise time LAT/ND fall time Symbol fX fBCX tWB tBr tBf tDS tDH tLS tLH tSHIFT tWS tSr tSf tWL tLP tLr tLf 300 300 100 100 20 20 50 50 1000 300 100 100 100 30 30 Conditions Ratings min typ 169 max 18.5 3.0 Unit MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Timing Chart
No. 5537-2/11
LC78857V Analog Characteristics at Ta = 25C, VDD = 5.0 V
Parameter Total harmonic distortion Signal-to-noise ratio Crosstalk Full scale output level Dynamic range Output load resistance Symbol THD+N S/N CT VFS DR RL 1kHz, 0 dB JIS-A 1kHz, 0 dB 1 kHz, 0dB JIS-A Pins 2 and 23 90 88 2.8 84 5 Conditions Ratings min typ 0.008 96 92 3.0 87 3.2 max 0.012 Unit % dB dB Vp-p dB k
Test Circuit
See the application circuit example PG: Pattern generator (signal generator) Filter: Band limiting filter
Block Diagram
Analog lowpass filter (left channel) PWM output circuit (left channel)
Analog lowpass filter (right channel)
PWM output circuit (right channel)
Noise shaper (left channel)
Noise shaper (right channel)
Mode control circuit
8 x oversampling digital filters
Timing generator
Interface circuit
Test circuit
No. 5537-3/11
LC78857V Pin Assignment
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol AVDDL OUTL AGNDL NC MODE SH/EMP LAT/ND DAT/MT BCLK DATA DGND DVDD LRCK XIN XOUT CKO INITB TEST NC AGNDR OUTR AVDDR Function Analog system power supply (left channel) Analog output (left channel) Analog system ground (left channel) No Connection Serial/parallel input mode selection When MODE is low: Control data shift signal (serial mode) When MODE is high: Emphasis on/off switching (parallel mode) When MODE is low: Control data latch signal (serial mode) When MODE is high: normal speed/double speed switching (parallel mode) When MODE is low: Control data input (serial mode) When MODE is high: Soft muting control input (parallel mode) Bit clock input Digital audio data input Digital system ground Digital system power supply LR clock input Crystal oscillator element input Crystal oscillator element output Clock output (384fs) Initialization signal input (The IC internal state is initialized on a low input.) Test pin (This pin must be connected to DGND during normal operation.) No Connection Analog system ground (right channel) Analog output (right channel) Analog system power supply (right channel)
No. 5537-4/11
LC78857V Circuit Operation The LC78857V consists of three main blocks: the digital filter block, the sigma-delta D/A converter block, and the analog filter block. [Digital Filter Block] The LC78857V performs the following calculations. * Normal speed mode:
Input
Attenuator
Deemphas is firstorder IIR filter
31st-order FIR filter
11th-order FIR filter
3rd-order FIR filter
To the sigma-delta D/A converter
* Double speed mode: This mode is used, for example, when dubbing a CD to cassette tape at double speed. Although the XIN has the same frequency as normal speed mode, BCLK, LRCK, and DATA are input at twice the rate used in normal speed.
Input
Attenuator
Deemphas is firstorder IIR filter
31st-order FIR filter
3rd-order FIR filter
To the sigma-delta D/A converter
fs* = double speed input = 2 x fs.
[Sigma-Delta D/A Converter Block] This circuit accepts 8fs data input and outputs a 384fs 1-bit data sequence.
From the digital filters
Front-end interpolation
3rd-order noise shaper
PWM D/A converter
1-bit output A 1-bit output B
[Analog Low-Pass Filter Block] This block consists of an analog low-pass filter that consists of on-chip resistors, capacitors, and operational amplifiers. This block converts the 384fs 1-bit data streams A and B directly to an analog voltage output.
1-bit output A
1-bit output B
No. 5537-5/11
LC78857V Input Setup 1. Digital audio data input The digital audio data is a 16-bit serial signal in an MSB-first two's complement format. The 16-bit serial data is input from the DATA pin to an internal register on the rising edge of the BCLK signal, and is read in on the rising and falling edges of the LRCK signal.
Digital Audio Data Input Timing
2. Mode setup The method used to set the speed (normal/double), deemphasis, and digital attenuator settings differs depending on the state of the mode pin (MODE). * When MODE is low: serial input mode In this mode, the speed (normal/double), deemphasis, and digital attenuator settings are set by inputting serial data to the DAT/MT pin.
Attenuator data
*: The SH/EMP signal may also have the form shown by the dotted line.
Notes:DAT/MT and SH/EMP: These pins must be held fixed (low or high) at all times other than the data transfer period (t1 in the figure). LAT/ND: This pin must be held high at all times other than during data acquisition.
* A0 (ND): Normal/double speed flag * A1 (EMP): Deemphasis flag
A0 (ND) L H Normal/double speed Normal speed Double speed A1 (EMP) L H Deemphasis Off On
The deemphasis function supports operation at fs = 44.1 kHz.
No. 5537-6/11
LC78857V * Attenuator data The signal can be attenuated by inputting attenuation data (A2 to A9). The attenuation specified by the attenuation data is given by the following formula: 20 * log Attenuation data ---------------- (dB) 128 Note: The attenuation is 0 dB when the data value is 7F (hexadecimal).
However, if A9 (the MSB) is 1, the A2 to A data is ignored and the prior attenuation setting is retained.
Attenuation data MSB A9 0 0 * * * 0 0 A8 1 1 * * * 0 0 A7 1 1 * * * 0 0 A6 1 1 * * * 0 0 A5 1 1 * * * 0 0 A4 1 1 * * * 0 0 A3 1 1 * * * 0 0 LSB A2 1 0 * * * 1 0 0 -0.137 * * * -42.14 - Attenuation level (dB)
If the attenuation level is changed from 0 dB to - dB, the IC performs a soft muting operation. The soft muting time is 1/Fs x 1024. Also, the time required to change the attenuation follows the slope of the soft muting function. If new attenuation data is input while the attenuation is changing, the attenuation level starts to change from the current level to the newly specified level at that point. Note: If the IC is initialized when the MODE pin is low, the IC is initialized with serial data values of A0 = A1 = A9 = low, and A2 to A8 = high. However, the LAT/ND must be held high during this initialization. * When MODE is high: parallel input mode In this mode, the speed (normal/double), deemphasis, and soft muting settings are specified with the LAT/ND, SH/EMP, and DAT/MT pins. It is not possible to set the attenuation data in this mode. * Normal speed/double speed setting
LAT/ND L H Normal/double speed Normal speed Double speed
* Deemphasis setting
SH/EMP L H Deemphasis Off On
The deemphasis function supports operation at fs = 44.1 kHz. * Soft muting setting The LC78857V uses the digital attenuator to implement a soft muting function. If the input level applied to the DAT/MT pin is changed from low to high, the attenuation changes from 0 dB to - dB. Inversely, if the DAT/MT pin is changed from high to low, the attenuation changes from - dB to 0 dB. The time required for the change is 1/fs x 1024.
DAT/MT L H
Soft muting Off On
No. 5537-7/11
LC78857V 3. Initialization This IC requires initialization when power is first applied and for system operation switching. After the power-supply voltage has stabilized and XIN, BCLK, and LRCK have been supplied, initialization is achieved by holding the INITB pin at the low level for at least one LRCK period as shown in the figure below. When INITB is low, the digital filter outputs and the noise shaper (sigma-delta D/A converter) internal states are all set to 0, and the analog outputs (OUTL and OUTR) go to the zero cross level.
Supply voltage
At least 1 LRCK period
System Clock The LC78857V operates from a 384fs system clock.
Crystal Crystal: 16.9344 MHz when fs = 44.1 kHz
The 384fs system clock is generated using a crystal oscillator circuit consisting of a crystal element, resistors, and capacitors as shown in the figure. Optimal values for the resistors and capacitances depend on the peripheral circuits and other conditions. The sigma-delta D/A converter is a sensitive circuit, and the analog characteristics are strongly influenced by the quality of the waveform (e.g. its jitter characteristics) of the system clock input to the XIN pin. When an external signal is input as the system clock, adequate care must be taken to assure the quality of this signal's waveform. * CKO: Outputs a clock signal with the same frequency as the signal input to the XIN pin. Digital Filter Characteristics 1. Frequency characteristics * Normal speed (deemphasis off)
Attenuation - dB
Sampling frequency, fs No. 5537-8/11
LC78857V * Double speed (deemphasis off)
Attenuation - dB
Sampling frequency, fs--Hz
2. Deemphasis on pass band characteristics * Normal speed (deemphasis on)
Attenuation - dB
Frequency--Hz
* Double speed (deemphasis on)
Attenuation - dB
Frequency--Hz
No. 5537-9/11
LC78857V Sample Application Circuit
Second order active low-pass filter
Notes: * All DVDD nodes in the circuit diagram must be connected to the digital system power supply, and all AVDD nodes must be connected to the analog system power supply. * Since latchup may occur if there is a discrepancy in the times at which the DVDD and AVDD voltages are applied, applications must be designed so that there is no time difference between the points when these voltages are applied. * If there is a potential difference between the DVDD and AVDD voltages, it must not exceed 0.3 V. * The application circuit example is an actual application circuit. Appropriate band limiting filters, which prevent adverse influence of band noise, are required to acquire the analog characteristics listed in the electrical characteristics.
No. 5537-10/11
LC78857V Power Supply Timing * The analog system power supplies (AVDDL and AVDDR) and the digital system power supply (DV DD) must be applied and cut at the same time. * If time lags between these power supplies are unavoidable, the timing must meet one of the following two conditions. (1) The power on (and power off) time lag must be under 3 ms as shown in figure 1. (2) If the time lag must be over 3 ms, then the rise time for the first power supply to be powered on (or powered off) must exceed 5 ms, and furthermore, the time difference must exceed 50 ms as shown in figure 2.
Under 3 ms
Under 3 ms
Figure 1
Over 5 ms Under 50 ms
Over 5 ms Under 50 ms
Figure 2
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. PS No. 5537-11/11

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